`timescale 1ps / 1ps
module npc(input [31:0]pc,
           input [31:0]Zero,
           input [2:0]Branch,
           input [1:0]Jump,
           input [31:0]imm32,
           input [31:0]busA,
           output reg [31:0]npc,
           output reg [31:0]Bnpc);

reg[31:0] tR;
reg signed [31:0]result;

always @(*) begin
    result     = imm32 * 4;
    tR         = Zero;
    npc        = pc + 4;
    Bnpc       = pc + 4;
    if (Branch == 3'b001 && tR == 0) npc = pc + 4 + result;
    if (Branch == 3'b010 && tR != 0) npc = pc + 4 + result;
    if (Branch == 3'b011 && tR >= 0) npc = pc + 4 + result;
    if (Branch == 3'b100 && tR > 0) npc = pc + 4 + result;
    if (Branch == 3'b101 && tR <= 0) npc = pc + 4 + result;
    if (Branch == 3'b110 && tR <  0) npc = pc + 4 + result;
    
    if (Jump == 1) npc = {pc[31:28],imm32[25:0]};
    if (Jump == 2) npc = busA;
end

endmodule // npc
